1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a programmable redundancy circuit and more particularly, to a structure of a redundancy decoder (spare decoder).
2. Description of the Prior Art
FIG. 1 is a diagram showing an example of a structure of a conventional semiconductor memory device.
Referring to FIG. 1, a plurality of word lines WL and a plurality of bit lines BL are arranged intersecting with each other. A spare word line SWL is arranged outside the plurality of word lines WL. A memory cell MC is provided at an intersection of each of the word lines WL and each of the bit lines BL. A spare memory cell SMC is provided at an intersection of the spare word line SWL and each of the bit lines BL. A plurality of row decoders 1 are provided corresponding to the plurality of word lines WL. Each of the row decoders 1 is connected to a corresponding word line WL through a word driver 2. In addition, a spare decoder 3 is provided corresponding to the spare word line SWL. The spare decoder 3 is connected to the spare word line SWL through a spare word driver 4. On the other hand, a plurality of column decoders 5 are provided corresponding to the plurality of bit lines BL.
Any of the row decoders 1 is selected in response to address signals A.sub.1, A.sub.1, . . . , A.sub.n. The selected row decoder 1 applies a predetermined selecting signal to a corresponding word driver 2. The word driver 2 is responsive to a word line driving signal .PHI..sub.X for forcing a corresponding word line WL to be a predetermined potential. Thus, a memory cell MC connected to the word line WL is selected. On the other hand, any of the column decoders 5 is selected in response to address signals B.sub.1, B.sub.1, . . . , B.sub.n. Thus, the bit line BL corresponding to the selected column decoder 5 is selected. As a result, a single memory cell MC is selected by the row decoder 1 and the column decoder 5. Information stored in the selected memory cell MC is read out or written to the selected memory cell MC.
Meanwhile, a defective memory cell may be produced in a manufacturing step. In this case, the spare word line SWL is selected in place of a word line WL connected to the defective memory cell. More specifically, when an address signal corresponding to the word line WL connected to the defective memory cell is applied, the spare decoder 3 is selected in place of a corresponding row decoder 1. The spare word driver 4 connected to the spare decoder 3 applies a predetermined potential to the spare word line SWL. Thus, if and when the address signal for selecting the defective memory cell is applied, a spare memory cell SMC is selected in place of the defective memory cell.
FIG. 2 is a diagram showing a specific circuit structure of main portions shown in FIG. 1. The circuit is described in, for example, an article entitled "A Low Power Sub l00ns 256K Bit Dynamic RAM", IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, October 1983, pp. 441-446.
Referring to FIG. 2, each of the row decoders 1 comprises an NOR circuit 11 having a plurality of input terminals. The NOR circuit 11 has one input terminal receiving a Normal Element Disable signal (NED signal) and other plurality of input terminals receiving address signals A.sub.1 or A.sub.1, A.sub.2 or A.sub.2, . . . , A.sub.n or A.sub.n, respectively. Each of the word drivers 2 comprises N channel MOSFETs 21 and 22. The MOSFET 21 is connected between an output terminal of the row decoder 1 and a gate of the MOSFET 22 and has its gate receiving a power-supply potential V.sub.CC. The MOSFET 22 has one conduction terminal receiving a word line driving signal .PHI..sub.X and other conduction terminal connected to a word line WL.
On the other hand, the spare decoder 3 comprises a plurality of N channel MOSFETs 31, a plurality of link elements 32 and N channel MOSFETs 33, 34 and 35. A plurality of serial circuits each comprising a link element 32 and an MOSFET 31 are connected between a node N1 and a ground terminal. Address signals A.sub.1, A.sub.1, . . . , A.sub.n and A.sub.n are applied to gates of the plurality of MOSFETs 31, respectively. In addition, the MOSFET 33 is coupled between the node N1 and the power-supply potential V.sub.CC and has its gate receiving a control signal .PHI..sub.p. The MOSFET 34 is connected between the node N1 and a gate of the MOSFET 35 and has its gate coupled to the power-supply potential V.sub.CC. The MOSFET 35 has one conduction terminal receiving a control signal .PHI..sub.C and other conduction terminal connected to a node N2. The above described NED signal is derived from the node N2. The spare word driver 4 comprises N channel MOSFETs 41 and 42. The MOSFET 41 is connected between the node N2 and a gate of the MOSFET 42 and has its gate coupled to the power-supply potential V.sub.CC. The MOSFET 42 has one conduction terminal receiving the word line driving signal .PHI..sub.X and other conduction terminal connected to a spare word line SWL.
If and when a defective memory cell exists of a plurality of memory cells MC, the link elements 32 in the spare decoder 3 are melted in advance by a laser beam or the like so that an address signal corresponding to a word line WL connected to the defective memory cell is applied.
Referring now to FIG. 3 of a waveform diagram, operation of the semiconductor memory device shown in FIGS. 1 and 2 is described.
Description is now made on a case in which an address signal corresponding to a word line WL connected to only a normal memory cell MC is applied.
The control signal .PHI..sub.p is at an "H" level, the control signal .PHI..sub.C is at an "L" level and the word line driving signal .PHI..sub.X is at the "L" level in a precharge (standby) period. At that time, since the MOSFETs 33, 34 and 35 are turned on, a potential of the node N2 is at the "L" level. Thus, the NED signal is at the "L" level. The control signal .PHI..sub.p falls to the "L" level, so that the MOSFET 33 is turned off. Then, address signals are applied to the input terminals of each of the row decoders 1. Only one of the row decoders 1 outputs a signal at the "H" level and the other row decoders 1 output a signal at the "L" level in response to the address signals. When all link elements 32 are not disconnected, a potential of the node N1 in the spare row decoder is at the "L" level. Then, the control signal .PHI..sub.C rises to the "H" level. However, since the MOSFET 35 is turned off, the potential of the node N2 does not change. Then, when the word line driving signal .PHI..sub.X rises to the "H" level, a potential on the word line WL corresponding to the row decoder 1 which outputs the signal at the "H" level rises to the "H" level.
Description is now made on a case in which the address signal corresponding to the word line WL connected to the defective memory cell is applied.
The control signal .PHI..sub.P is at the "H" level, the control signal .PHI..sub.C is at the "L" level, the word line driving signal .PHI..sub.X is at the "L" level and the NED signal is at the "L" level in a precharge period. Then, the control signal .PHI..sub.P falls to the "L" level, so that the MOSFET 33 is turned off. The address signals are applied to the row decoder 1 and the spare decoder 3. Consequently, the row decoder 1 corresponding to the word line WL connected to the defective memory cell outputs the signal at the "H" level. At that time, since all of the MOSFETs 31 connected to the link elements 32 which are not melted in the spare decoder 3 are turned off, the potential of the node Nl remains at the "H" level. Thus, the MOSFET 35 remains in the on-state. Then, when the control signal .PHI..sub.C rises to the "H" level, the potential of the node N2 attains the "H" level and the NED signal attains the "H" level. Consequently, the MOSFET 42 in the spare word driver 4 is turned on and outputs of all of the row decoders 1 attain the "L" level. Thus, when the word line driving signal .PHI..sub.X rises to the "H" level, a potential of only the spare word line SWL rises to the "H" level. In the above described manner, the spare word line SWL is selected in place of the word line WL connected to the defective memory cell.
In the conventional semiconductor memory device, since the area occupied by a spare decoder is increased, as compared with the normal decoder, the size of the entire semiconductor memory device is increased and the layout becomes difficult if a number of spare decoders are arranged.
The structure of a redundancy circuit provided in a charging path of a decoder comprising a link which can be melted by a laser is disclosed in U.S. Pat. No. 4,635,232 entitled "Semiconductor Memory Device". In addition, it is disclosed in U.S. Pat. No. 4,494,220 entitled "Folded Bit Line Memory with One Decoder per Pair of Spare Rows" that a link for disconnecting a defective word line is provided for each word line. Furthermore, it is disclosed in U.S. Pat. No. 4,658,379 entitled "Semiconductor Memory Device with a Laser Programmable Redundancy Circuit" that a link for lnactivating a decoder corresponding to a defective memory cell is provided in a charging path in each decoder when the defective memory cell exists.